Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
Another goal of semiconductor manufacturing is to reduce cost and increase yields. Conventional semiconductor devices often contain semiconductor die mounted to semiconductor substrates. Because a significant portion of packaging costs are related to the costs associated with semiconductor substrates, improvements to substrate design and manufacturing further the goal of reducing costs and increasing yields. One source of decreased yields and increased manufacturing costs for substrates is excessive substrate warpage.
Accordingly, FIGS. 1a-1c serve as illustrations of substrates with excessive warpage. FIG. 1a shows a conventional semiconductor substrate or carrier used for mounting semiconductor devices. Substrate 10 can be silicon, germanium, gallium arsenide, indium phosphide, silicon carbide, polymer, beryllium oxide or other suitable rigid material for structural support. A plurality of openings or vias 12 is formed through substrate 10 using laser drilling, mechanical drilling, deep reactive ion etching (DRIE) or other suitable process.
An insulating or passivation layer 14 is formed on substrate 10. Insulating layer 14 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties, and is formed using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation.
Conductive layer 16 is formed on insulating layer 14 and over substrate 10 and vias 12 to form intermediate substrate or carrier 18. Conductive layer 16 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material formed by electrolytic plating or electroless plating for electrical interconnect. In one embodiment, conductive layer 16 is Cu foil disposed on substrate 10 and insulating layer 14 with a hot lamination process.
In one embodiment, intermediate substrate 18 is formed in a double substrate process where first and second substrates 10 are mounted together with an interface layer, double-sided tape, thermal release layer, or other suitable material as a temporary adhesive bonding film. Vias 12, insulating layers 14, and conductive layers 16 are formed for both first and second substrates 10 while first and second substrates 10 are mounted together with the temporary adhesive bonding film. First and second substrates 10 can also undergo a full surface etching to remove a surface Cu layer that may be present on substrates 10. The removal of the temporary adhesive bonding film results in first and second intermediate substrates 18.
FIG. 1b shows an exaggerated view of the warpage W that can occur to intermediate substrate 18, including the warpage that results from separation of the intermediate substrate in a double substrate process. As shown in FIG. 1b, the warpage W is measured as the vertical displacement from the periphery of the intermediate carrier to the center of the intermediate carrier. While a double substrate process is employed to reduce warpage of intermediate substrate 18 during the formation of vias 12, insulating layer 14, and conductive layer 16, intermediate substrates 18 are subject to warpage upon splitting the intermediate carriers from each other at removal of the temporary adhesive bonding film. Warpage occurs because conductive layer 16 produces a high volume of conductive material, such as Cu, on only one side of the intermediate carrier. In one embodiment, intermediate substrate 18 has a warpage W of 2 centimeters (cm) after patterning of conductive layer 16 and further has a warpage W of 4.5 cm after both the patterning of conductive layer 16 and the formation of vias 12.
FIG. 1c shows an exaggerated view of the warpage of a final substrate or printed circuit board (PCB) 22 similar to the warpage of intermediate substrate 18 shown in FIG. 1b. In FIG. 1c, conductive layer 16 is patterned and a portion of the conductive layer is removed according to the design and function of final substrate 22. An insulating or passivation layer 24 is conformally applied over intermediate substrate 18 using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. Insulating layer 24 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. In one embodiment, insulating layer 24 includes a photo-sensitive resist. Insulating layer 24 follows the contours of intermediate substrate 18 and is patterned such that a portion of the insulating layer is removed to form openings 26 to expose portions of conductive layer 16 for subsequent electrical interconnect.
FIG. 1c further shows vias 12 are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), poly-silicon, or other suitable electrically conductive material using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process to form conductive vias 28. The formation of conductive vias 28 can also include the steps of forming and of patterning masking layers as needed.
The formation of final substrate 22 with a high volume of conductive material on only one side of the substrate produces a decreased yield of viable substrates resulting from excessive warpage. Increases in yield loss are generally greater for one level or single level substrates than for multiple level or two level substrates. In fact, increases in yield losses are also present for applications involving flexible ball grid arrays (FBGAs). Yield losses due to excessive warpage for one level substrates in FBGA applications increase on the order of thirty percent with respect to two level substrates in FBGA applications. However, reliance on two level FBGAs to offset the reduced yields of one level FBGAs increases cost through additional or more involved process steps, such as laser drilling. Thus, applications for two level and multilevel FBGA applications are more time intensive and expensive than applications for one level FBGAs.